Transactor-based Prototyping of Heterogeneous Multiprocessor System-On-Chip Architectures
نویسندگان
چکیده
We present the prototyping of a heterogeneous multiprocessor system-on-chip (MPSoC) design, which consists of general purpose RISC processors as well as novel accelerators in form of tightly-coupled processor arrays (TCPA). In general, TCPAs are well suited to accelerate numerous compute-intensive tasks such as video and other digital signal processing. We consider a transactor-based co-design approach where the TCPA is implemented on a CHIPit system and performs image processing of video data in real-time, whereas parts for control and configuration management of the MPSoC are realized in software on the host PC. For interaction between the two parts, the Synopsys Transactor Reference Library is used. The design employs an AHB bus where some components are in the FPGA whereas other components are implemented in software and are communicating to the bus using AMBA transactors. This co-design approach significantly reduces design time when evaluating architecture alternatives.
منابع مشابه
FPGA Prototyping and Design Evaluation of a NoC-Based MPSoC
Chip communication architectures become an important element that is critical to control when designing a complex MultiProcessor System-on-Chip (MPSoC). This led to the emergence of new interconnection architectures, like Network-on-Chip (NoC). NoCs have been proven to be a promising solution to the concerns of MPSoCs in terms of data parallelism. Field-Programmable Gate Arrays (FPGA) has some ...
متن کاملReliability and Performance Evaluation of Fault-aware Routing Methods for Network-on-Chip Architectures (RESEARCH NOTE)
Nowadays, faults and failures are increasing especially in complex systems such as Network-on-Chip (NoC) based Systems-on-a-Chip due to the increasing susceptibility and decreasing feature sizes. On the other hand, fault-tolerant routing algorithms have an evident effect on tolerating permanent faults and improving the reliability of a Network-on-Chip based system. This paper presents reliabili...
متن کاملA Routing-Aware Simulated Annealing-based Placement Method in Wireless Network on Chips
Wireless network on chip (WiNoC) is one of the promising on-chip interconnection networks for on-chip system architectures. In addition to wired links, these architectures also use wireless links. Using these wireless links makes packets reach destination nodes faster and with less power consumption. These wireless links are provided by wireless interfaces in wireless routers. The WiNoC archite...
متن کاملCritical Block Scheduling: A Thread-Level Parallelizing Mechanism for a Heterogeneous Chip Multiprocessor Architecture
Processor-in-Memory (PIM) architectures are developed for highperformance computing by integrating processing units with memory blocks into a single chip to reduce the performance gap between the processor and the memory. The PIM architecture combines heterogeneous processors in a single system. These processors are characterized by their computation and memoryaccess capabilities. Therefore, a ...
متن کاملA model-based software implementation tool for multiprocessor embedded systems
We apply a formal, automated model-based design tool for synthesizing correct-by-construction parallel implementations of an MPEG-4 video encoder. The tool allows for early prototyping, verification and simulation of embedded applications. The generated software implementations are multi-threaded and customized for system on-chip multi-processor architectures. We consider two HW platforms: a cu...
متن کامل